Method of making semiconductor devices



y 1965 w. M- WEBSTER, JR 3,196,058

METHOD OF MAKING SEMICONDUCTOR DEVICES s Sheets-Shea 1 Original FiledAug. 24, 1959 vim c! m/ro 11 4/27 Di/VS/ T) J y 0, 1965 w. M. WEBSTER,JR 3,196,058

METHOD OF MAKING SEMICONDUCTOR DEVICES Original Fil ed Aug- 24, 1959 3Sheets-Sheet 2 July 20, 1965 w. M. WEBSTER, JR 3,

mm'non OF MAKING smmzconnucwon DEVICES ori inal Filed Aug. 24, 1959 sSheets- Sheet s Em I mm M s. 7W Z W MM MWM M Mm United States Patent3,196,058 METHQD 0F MAKENG SEMECGNDUCTOR DEVICES William M. Webster,Era, Princeton, Ni, assiguor to Radio {Iorporation of America, acorporation of Delaware Original application Aug. 24, 1959, Ser. No.835,577, now latent No. 3,0l6,7i, dated Oct. 31, 1961. Divided and thisapplication Feb. 6, 1961, Se No. 37,367

4 Claims. ((Il. 148-136) This application is a division of applicationSerial No. 835,577, filed August 24, 1959, and issued October 31, 1961,as US. Patent 3,006,791.

This invention relates to improved semiconductor devices, and moreparticularly to improved junction devices and methods of making them.

Junction devices contain at least one rectifying barrier at theinterface or junction between two regions which differ in type ormagnitude of conductivity. The barrier may be of the limited area type,such as point contact or line contact devices. Alternatively, thebarrier may be of the broad area type, such as surface alloyedjunctions, grown junctions, and diffused junctions.

Junctions are called abrupt when the conductivity type changes veryrapidly over a small distance which may be of the order of the depletionlayer thiclmess, while junctions in which the conductivity type changesmore slowly over a several-fold greater distance are known as gradualjunctions.

The device known as the junction transistor comprises a body ofmonocrystalline semiconductive material including a zone or region ofgiven conductivity type between two adjacent spaced regions of oppositeconductivity type. Junctions are formed between the intermediate zoneand each spaced region. In such units, one of the two spaced regions isknown as the emitter, the other as the collector, and the intermediategiven conductivity type zone as the base.

The electrical characteristics of junction devices such as transistorsare dependent on many factors, among which the distribution of mobilecharge carriers in the various portions of the unit is critical. Themobile charge carrier distribution is dependent on the concentration ofthe conductivity type-determining substance or ionized active impurityatoms in the semiconductor.

Another important factor is the abruptness of the emitter-base andbase-collector junctions. For example, it is found that surface alloyingproduces abrupt junctions, while grown junction techniques producegradual junctions. Diffused junctions are somewhat intermediate as toabruptness; when formed at low temperatures using a low concentrationimpurity source, diffused junctions are gradual; when formed bydiffusion at high temperatures from a concentrated impurity source,diffused junctions are more abrupt.

Transistors with different characteristics may thus be prepared bychanging the impurity density profile and by forming either abrupt orgradual emitter-base and basecollector junctions. For a more completediscussion and listing of various impurity density profiles, with thecorresponding transistor types which may thus be made, see P. Kaufmannand G. Freedman, An Analysis of Impurity Distributions and TheirRelations to Electrical Behavior of Conventional TransistorConstructions, Semiconductor Products, April 1959.

For many applications, such as deflection circuits in televisionreceivers, it is desirable to utilize transistors which can withstand ahigh reverse voltage without breakdown. It is also desirable that thesetransistors transmit relatively high currents, and act as a rapidswitch. In order to withstand high reverse voltages, for example areverse bias of over 100 volts in germanium transistors,

3,l%,d58 Patented July 20, 1965 the collector junction should begradual, and the resistivity of that portion of the collector regionimmediately adjacent the base-collector junction should be high. Inorder to handle high currents, that portion of the collector regionremoved from the base-collector junction should have high conductivity,i.e., low resistivity.

Grown junction techniques give a gradual base-collector junction, butthe resistivity of the collector region is too igh. Surface alloyed orfused junctions give a low resistivity collector region, but thebase-collector junction is abrupt and hence unable to withstand a highreverse bias. A conventional diffused collector junction will havecharacteristics somewhere between those of an alloy junction and a grownjunction, but, at best, is an unsatisfactory compromise, since, if thediffused base-collector junction is gradual, the resistivity of thecollector region is too high, while, if diffusion is performed undersuch conditions as to produce a low resistivity collector region, thenthe base-collector junction is too abrupt. Therefore, the simultaneousrequirements of a high conductivity collector region and a gradualbase-collector junction in the same device are diflicult to attain.

Attempts have been made to solve this problem by means of the grownjunction technique. F or example, the collector region is grown insteps, as described, for example, in US. Patent 2,878,152, by growing aportion of a silicon transistor bar from a melt, then adding a certainamount of impurity to the melt, growing the next portion of the bar,placing more impurity in the melt before growing another portion, thenadding still more impurity to the melt before growing the last portionof the bar. The collector region of such grown junction transistors hasa low conductivity portion adjacent the base, and a high conductivityportion removed from the base, but the conductivity of each saidcollector portion is relatively constant, i.e., the collector region asa whole is not continuously graded. Moreover, the base region of such adevice is of substantially constant medium resistivity, whereas acontinuously graded base of high resistivity offers better results athigh frequencies. Another problem arises, since the emitter-basejunction and the base-collector junction are both formed by the samegrown junction technique; they are therefore both equally abrupt orequally gradual, whereas, as discussed above, it is preferable that thetwo junctions differ in this respect.

Attempts have also been made to fabricate high speed transistors by acombination of in-dilfusion, out-diffusion, and alloying techniques. Forexample, an active impurity is diffused into a given conductivity typesemiconductive wafer to convert a surface region thereof to oppositeconductivity type. Thereafter the wafer is heated in a vacuum, asdescribed in US. Patent 2,810,870, to outditiuse a portion of theaforesaid active impurity from the surface of the wafer. Subsequently, aportion of the wafer is removed, so that the remainder consists of a P-type layer and an N-type layer. Next, impurity dots of the sameconductivity type are fused or alloyed to the opposite major faces ofthe wafer. Devices thus fabricated include a graded resistivity baseregion. However, in the collector region of such devices the resistivitydecreases with distance from the junction to a value which remainsconstant throughout the remainder of the collector region. In otherwords, the collector region is not continuously graded. Moreover, themethod requires a complicated process of establishing the junctionlocation in the semiconductor wafer, then grinding and etching the waferto establish the desired base thickness. Furthermore, the formation oflarge area fused junctions with the required degree of precision anduniformity is a diflicult problem.

As a result of all these problems, germanium transistors which canhandle currents as high as 20 amperes and withstand reverse bias of over200 volts have not hitherto been reported.

An object of this invention is to provide improved semiconductordevices.

Another object of the invention is to provide improved methods of makingimproved semiconductor devices. Still another object is to provideimproved semiconductor devices capable of withstanding high reversevoltages. 1 Q

But another object is to provide improved semiconductor devices capableof switching high currents at high speeds.

Yet another object is to provide improvedsemiconductor devices capableof withstanding high reverse voltages and switching high currents athigh speeds.

These and other objects are accomplished by providing a transistor whichcomprises a low resistivity emitter region, an abrupt emitterbasejunction, a high resistivity base region, a gradual base-collectorjunction, and a collector region in which the resistivity iscontinuously graded and decreases with increasing distance from the baseregion. Such devices may be prepared starting with a given conductivitytype monocrystalline semi-conductive wafer having two opposed majorfaces, and slowly diffusing an active impurity which induces theopposite conductivity type into at least one major face of the wafer soas to convert a surface zone thereof to opposite conductivity and form agradual junction therein. A second diffusion is now performed under suchconditions as to convert a thin surface region on both major wafer facesto high conductivity'of the opposite conductivity type. A portion of thehigh conductivity region is removed. Leads may now be attached to eachmajor wafer face, and to the given conductivity type region between saidfaces. The resultant transistor has both high current transmittingcapacity and the capacity of switching the high current at high speed.

The invention will be described in greater detail with reference to theaccompanying drawing, in which:

FIGURE 1 is a diagram showing the idealized impurity density profiles ina typical surface alloyed transistor and in a single-diffused transistoraccording to the prior art;

FIGURE 2 is a diagram showing the idealized impurity density profile ina transistor according to the invention;

FIGURES 3a-3d are sectional views and FIGURE Be is a perspective viewrespectively illustrating successive steps in the fabrication of asemiconductor device in accordance with the invention; and,

FIGURE 4 is a diagram showing an idealized impurity density profile in asemiconductor body at one stage in the process of FIGURE 3.

In FIGURE 1, curve It represents the impurity density profile of asurface alloyed transistor. The curve It is a plot of the net impuritydensity, which is defined as the excess of the number of donor atoms Nover the number of acceptor atoms N per cmfi, against increasingdistance into the semiconductor wafer, i.e., for a transverse sectionacross the wafer. At the compensated level, the number of donor atomsequals the number of acceptor atoms, so that the portions of the waferat this level are neither N-type nor P-type. Above the compensatedlevel, the excess of donors over acceptors increases, with thesemiconductor going from N to N Below the compensated level, the excessof acceptors over donors increases, with the semiconductor going from Pto P Starting at the axis representing a major crystal surface, thecurve ltl crosses the compensated level twice, first at the transistionregion between the N-type emitter region and the P-type base region, andsubsequently at the transition region between the P-type base region andthe N-type collector region. The curve starts at a, at a high netimpurity density of N+ concentration. The emitter-base rectifyingbarrier or PN junction is formed at the first transition region b, wherethe curve suddenly drops to a P value. The base-collector PN junction isformed at the second transition region 0, where the curve suddenlyincreases again to a high net impurity density before terminating at a.The portion of curve 19 between a and b corresponds to the emitterregion; the portion of the same curve from b to c corresponds to thebase region; and the portion at corresponds to the collector region. Thecollector region cd has a high donor concentration, and its resistivityis low, and hence it can conduct high currents. However, thebase-collector junction is abrupt, so that the junction breaks down whenhigh reverse voltages of the order of volts and over are appliedthereto. Surface alloyed transistors having the characteristics of thecurve 10 are made, for example, by fusing or alloying lead-antimonyelectrode pellets to opposite major faces of a P-conductivity typegermanium wafer.

Curve 12 in FIGURE 1 shows the impurity density profile of a diffusedtransistor, which may, for example, be fabricated by diffusingphosphorus into a P-type silicon wafer, or diffusing arsenic into aP-type germanium wafer. In curve 12, a'b' represents the impurityconcentration in the emitter region, b'c represents the impurityconcentration in the base region, and cd' represents the impurityconcentration in the; collector region. In this diffused transistor thebase-collector junction is gradual, and hence the junction withstandsrelatively high reverse voltages before breaking down. However, theconcentration of impurity atoms in the collector region, and hence thecollector conductivity, is not as high as in the alloyed devicerepresented by curve 10. Accordingly, the collector region of thediffused unit does not handle as high currents. The base-collectorjunction of the diffused unit can be made more gradual by adjustingtemperatures and utilizing low concentration impurity sources for thediffusion step, but making the base-collector junction more gradualreduces the conductivity of the collector region. Alternatively, byusing high concentration impurity sources for the diffusion step, thecollector region of the diffused unit is made more conductive, but thishigh concentration of impurity sources makes the basecollector junctionmore abrupt. Thus, the impurity distribution in such a single-diffusedunit at best is a compromise which does not fully provide both a highcurrent handling capacity and a high reverse-voltage breakdowncharacteristic. j

Referring to FIGURE 2, curve 249, represents the im purity densityprofile in a semi-conductor device according to the invention. Theprofile is that of a transverse section from a metallic ohmic emittercontact across the emitter, base and collector regions to an ohmicmetallic collector contact. The curve illustrated is that for an NPNtransistor, as are each of the curves 1t and 12 in FIGURE 1, but it willbe understood that this is by way of illustration only, since PNP unitsmay be fabricated with similar characteristics for reverse polarityvoltages by reversing the conductivity types of the various deviceportions. The impurity density profiles of the corresponding PNP deviceswould simply be reversed or symmetrically reflected around thecompensated level. i

It will be appreciated that the transistor of curve 20 comprises a highconductivity emitter region represented by the portion a"b" of curve 20,and an abrupt emitterbase junction represented by the portion of thecurve around b", which combination provides good injection efficiency; alow conductivity base region represented by the portion b"c" of curve 20graded to lower conductivity adjacent the collector, thus providingimproved performance at high frequencies; a gradual base-collectorjunction represented bythe portion of the curve around 0 and acontinuously graded collector region represented by the.

portion c"d" of curve 2% having high conductivity in the portion of thecollector remote from the base-collector junction, which combinationprovides the ability to withstand high reverse voltages and to transmithigh currents. The device of curve 24) thus combines the advantages of as eep-es high conductivity collector region, as in alloyed units, withthe advantages of a gradual base-collector junction, as in diffusedunits.

The impurity density distribution represented by curve may be achieved,for example, by starting with a given conductivity type monocrystallinesemiconductive wafer having two opposed major faces, the wafer beingabout twice as thick as that ultimately desired. The wafer initially hasa uniform low resistivity, and may for example be of P-conductivitytype, as illustrated in FIGURE 4. Thereafter, a type-determiningsubstance which induces opposite conductivity type in the semiconductorselected, and is also known as an active impurity, is diffused into thewafer to form a surface zone of opposite conductivity type. In thisexample, since the wafer is initially P-type, the active impurity is adonor. This diffustion step is performed under such conditions oftemperature and low impurity source concentration as to form a gradualjunction all around the wafer interior. The resulting impurity densitydistribution is shown by curve in FIGURE 4. Next, the wafer is reducedfrom one major face to about half its initial thickness, therebyremoving the aforesaid surface zone adjacent said one major face. Theimpurity density curve in the remaining half of the wafer is the portionAB, and this curve is exactly the same as curve AB of FIGURE 2, the onlydifierence being an enlargement of scale in FIGURE 2 for greaterclarity.

A second diffusion step is performed on the remaining half of the wafer.Again a donor is diffused into the wafer, but in the second diffusionstep the parameters of difiusion temperatures, diffusion time, andimpurity source concentration are adjusted to produce a thin surfaceregion which is strongly N-type and hence exhibits high conductivity.The low impurity concentration near each major wafer face, which isshown by the dashed portions of the curve in FIGURE 2 as lightly P-typeat A and lightly N-type at B, is thus completely overwhelmed by thesecond diffusion step. The combination of the two separate steps resultsin the impurity density profile depicted by the solid curve 20 in FIGURE2. The unit is completed by removing a portion of said high conductivityregion, and attaching leads to each major face and to the givenconductivity region between said faces. The device thus formed comprisesa heavily doped emitter region, an abrupt emitter-base junction, alightly doped graded base region, a gradual base-collector junction, anda continuously graded heavily doped collector region in which theportion remote from the base-collector junction is more heavily dopedthan the portion adjacent said junction.

Alternatively, one major face of the semiconductor wafer may be masked,and a type-determining impurity diffused into the other major face undersuch conditions as to form a single gradual junction in the wafer. Theimpurity density profile will then resemble portion AB of curve 40 inFIGURE 4. Thereafter the mask is removed, and a second diffusion step isperformed with the same impurity, or with one which induces the sameconductivity type, so that the resulting impurity density distributionresembles curve a"b"c"d" in FIGURE 2.

Since the particular advantages of the instant invention are obtained bytwo successive diffusion steps, in which an active impurity of the sameconductivity type is difiused into the semiconductor body during eachdiffusion step, devices made according to the instant invention aredistinguished from so-called double-diffused devices. The termdouble-diffused has become associated in the art with the simultaneousor successive diffusion of two active impurities of oppositeconductivity type, e.g., the simultaneous diffusion of an acceptor and adonor into a semiconductive body.

A preferred example will now be given illustrating the preparation of abroad area germanium junction triode of the NPN type in accordance withthe present invention. However, it is to be understood that by utilizingappropriate active impurities the method is equally applicable in makingPNP devices, and that other crystalline semiconductors such as silicon,silicon-germanium alloys, and compounds such as the phosphides,arsenides, and antimonides of aluminum, gallium, and indium may beutilized instead of germanium.

Example FIGURE 3:: is a sectional view of a monocrystallinesemiconductor wafer 3% having two opposed major faces. In this example,wafer 30 consists of P-type germanium having a resistivity of about 1 to20 ohm centimeters. The exact wafer dimensions are not critical. In thisexample, germanium wafer 30 is about 300 mils square and 6 mils thick.One major wafer face is masked by means of a coating 31 which ispractically impervious to the subsequent diifusion of active impurities.A suitable coating for this purpose may be formed by heating the waferin the vapors of an organic siloxane compound at a temperature below themelting point of the semiconductor but above that at which the siloxanedecomposes, so that an inert adherent coating of silicon oxide is formedon the wafer surface. In this example, the wafer 30 is heated from 10-15minutes at about 700 C. in a quartz furnace containing triethoxysilane,using argon as the carrier gas to sweep the siloxane fumes through thefurnace. The coating 31 will thus cover the entire wafer, but may bereadily removed from one major wafer face by washing that one face with5% hydrofluoric acid. Alternatively, one wafer face may be waxed down ona glass slide prior to the siloxane treatment, so that the adherentcoating 31 is formed only on the exposed major wafer face. The wax issubsequently removed by an organic solvent, such as trichlorethylene.

Referring now to FIGURE 35, a conductivity type-determining substance,which in this example is a donor, is diffused into the masked wafer 30by any convenient method. The impurity diffuses into the unmasked majorface at least two orders of magnitude more rapidly than it diffusesthroughout the coating 31, hence an impurity-diffused N-type zone 32 isformed adjacent the uncoated major face of the wafer. A rectifyingbarrier or PN junction 34 is thereby fabricated at the interface betweenthe impurity-difiused N-type surface zone 32 and the remaining P-typeportion 33 of the wafer.

A suitable method of diffusing an active impurity such as a donor or anacceptor into germanium wafers is described in US. Pat. No. 2,870,050,issued January 20, 1959 to C. W. Mueller et al. and assigned to theassignee of this application. In this example, the germanium wafer 30 isimmersed in a powder composed of germanium which has been doped with4X10 antimony atoms per cm. The Wafer is heated for one hour at about800 C. while immersed in the powder. The antimony diffuses into theunmasked face of the germanium wafer about 0.3 mil deep during thisstep, but practically no antimony diffuses into the masked wafer faceunder these conditions. The wafer is then cooled, removed from thepowder, and reheated for 20 hours at 850 C. in a nitrogen atmosphere.During this step the antimony is driven into the wafer to a depth ofabout 3 mils, and a shallow impurity gradient is produced. Theconcentration of antimony in the source powder, the furnace temperature,and the duration of the heating steps are adjusted to produce aconcentration of about 10 atoms of antimony per cm. on the wafersurface. Under these conditions of a small impurity gradient, theantimony impurity density profile of wafer 30 is similar to that shownin portion AB of the curve in FIGURE 4, and the rectifying barrier or PNjunction 34 is formed about 3 mils below the wafer surface. Junction 34thus formed is so gradual as to exhibit a high breakdown voltage.

Referring now to FIGURE 3c, the masking coating 31 is removed by washingthe wafer 30 in 5% hydrofluoric acid, and a second diffusion step isperformed on the wafer. This time the parameters of sourceconcentration, temperature, and time infurnace are adjusted to give alarge impurity density gradient. In this example, the second diffusionstep is accomplished by heating wafer30 in a nitrogen-swept furnace forabout one hour at 800 C. while the wafer is immersed in a powdercomposed of 95% germanium and arsenic by weight. A thin surface region35 of wafer 30 is thereby heavily doped with arsenic and thus convertedto N+ conductivity type. The concentration of arsenic in the wafersurface after this step is about 10 atoms per crnfi.

Next, the ends of wafer are removed, leaving the wafer with successivelayers, from the bottom as viewed in FIGURE 3d, of N N, P, and N+conductivity. The removal of the ends may be accomplished by grindingwheels, cutting tools, lapping techniques, or masking and etchingmethods. In'this example, portions of the wafer are covered with an acidresist such as wax, and the remainder is removed by an etchantconsisting of a mixture of hydrofluoric and nitric acids. The removal ofthe wafer ends divides the N+ reg-ion into two separate zones. -One zone35 is. adjacent the N-type zone 32, while the other zone or layer, whichis marked 35' in FIGURESd, is adjacent the P-type zone 33.

To facilitate the fabrication of a base contact, it is convenient duringthe same etching step to remove a portion of that N+ zone 35' which isadjacent to P layer 33. In this example, the remaining portion of theetched N+ layer 35 is a disc-shaped mesa or plateau '37 with a diameterof about 225 mils. This mesa 3'7 becomes the emitter region of thedevice. It will be seen that in the collector region of the device,which is the region below base-collector junction 34, the portion 35remote from the base-collector junction 34 is more heavily doped withactive impurity (arsenic'in this example) than the antimony-dilfusedN-type portion 32 adjacent to the basecollector junction 34. Referringnow to the perspective view in FIGURE 3e, the semiconductor wafer 30 issoldered down to a copper header 14 which serves as a heat sink, andalso becomes the collector connection. The header or mounting base 14contains two stem leads 15 and 16 which are insulated from the header.For convenience, the base also contains a threaded portion 17 tofacilitate subsequent insertion of the device into a tapped hole in achassis. The wafer 30 is soldered to the header in this example by meansof a lead-antimony solder, with the disc-shaped emitter mesa 37uppermost. Emitter connector 18 is a metal tab on one stem lead 15 whichis soldered to the N+ upper surface of the mesa 37. In this example, theemitter connection 18 is composed of nickel or nickel alloys coated withlead-tin solder. Base connector 19 is a metal tab mounted on the otherstem lead 16 and terminating in a ring 13 which is soldered to the uppersurface of the P-type base region of the wafer around mesa 37. In thisexample, the base connection 19 is composed of nickel coated withindium. The device may thenbe encapsulated and cased by known methods.

An advantage of devices according to the invention is the high emitterinjection efliciency obtained by the juxtaposition of a highconductivity emitter region with a low conductivity base region. Anotheradvantage is that the concentration of active impurity atoms in the baseregion is graded from higher adjacent the emitter to lower adjacent thecollector. Such grading produces a built-in .field which accelerates thepassage of minority charge carriers from the emitter across the baseregion to the collector, and thereby increases the high frequencyresponse of the unit. Furthermore, the high conductivity of the portionof the collector region remote from the base enables the device tohandle currents as large as 20 amperes, while the continuous grading ofthe collector region and the gradual base-collector junction enables thedevice to withstand high reversevoltages without breakdown. ConventionalNFN germanium transistors break down when the applied reverse collectorbias reaches 60 to volts. In contrast, transistors according to theinvention withstand a reverse voltage of 400 volts and higher withoutbreakdown. Some germanium NPN units made according to the invention asdescribed in connection with FIGURE 3 have exhibited both the ability tohandle 20 ampere currents and a reverse breakdown voltage as high as 700volts.

What is claimed is: 1. A method of fabricating a high breakdown voltagetransistor comprising the following steps:

preparing a given conductivity type monocrystalline semiconductive waferwith two opposed major faces and two wafer ends; diffusing an activeimpurity into said Wafer at a first and slow rate from a first and lowconcentration impurity source maintained at a first and low temperatureso as to convert a surface zone thereof all around said wafer toopposite conductivity type and form a gradual junction therein; 7reducing the wafer thickness from one said major wafer face to abouthalf the original wafer thickness; diffusing an active impurity intosaid wafer at a second rate greater than said first diffusion rate froma second impurity source at a second concentration higher than saidfirst impurity source concentration and maintained at a secondtemperature higher than said first source temperature so as to convert athin surface region on both said major wafer faces to conductivity ofsaid opposite conductivity type but higher conductivity than saidsurface zone; removing the wafer ends to divide the said higherconductivity surface region into two separate zones adjacent said twomajor wafer faces; removing a peripheral portion of the highconductivity surface region adjacent the given conductivity type regionof said wafer to expose a portion of said given conductivity typeregion; and, attaching leads to the remaining portion of each major faceand to said exposed portion of said given conductivity type region. 2. Amethod of fabricating a high breakdown voltage transistor comprising thefollowing steps:

preparing a given conductivity type monocrystalline semiconductive waferwith two opposed major faces and two wafer ends; masking one major faceof said wafer; diffusing an active impurity into the unmasked majorwafer face at a first and slow rate from a first and low concentrationimpurity source maintained at a first and low temperature, so as toconvert a surface zone thereof to opposite conductivity type and form agradual junction therein; removing the mask from said one major waferface; diffusing an active impurity into said wafer at a second rategreater than said first diffusion rate from a second impurity source ata second concentration higher than said first impurity sourceconcentration and maintained at a second temperature higher than saidfirst impurity source temperature so as to convert a thin surface regionon both major wafer faces to conductivity of said opposite type, buthigher conductivity than said surface zone; removing the wafer ends todivide the said higher conductivity surface region into two separatezones adjacent said two major wafer faces; removing a peripheral portionof said high conductivity surface region adjacent the given conductivitytype region of said wafer to expose a portion of said given conductivitytype region; and, attaching leads to the remaining portion of each majorface and to said exposed portion of said given conductivity type regionof said wafer.

9 3. A method of fabricating a high breakdown voltage transistorcomprising the following steps:

preparing a given conductivity type monocrystalline semiconductive waferwith two opposed major faces and two wafer ends;

masking one major face of said wafer;

diffusing an active impurity into the unmasked major Wafer face at afirst and sl w rate from a first and low concentration impurity sourcemaintained at a first and low temperature so as to convert a surfacezone thereof to opposite conductivity type and form a gradual junctiontherein, said first impurity source concentration and said firstimpurity source temperature being sufiicient to produce an impurity atomconcentration of about 10 impurity atoms per cm. on the surface of saidunmasked wafer face;

removing the mask from said one major Wafer face;

diffusing an active impurity into said wafer at a second rate greaterthan said first difiusion rate from a second impurity source at a secondconcentration higher than said first impurity source concentration andmaintained at a second temperature higher than said first impuritysource temperature so as to convert a thin surface region on both majorfaces to conductivity of said opposite type but higher conductivity thansaid surface zone, the concentration and temperature of said secondimpurity source being sufiicient to produce an impurity atomconcentration of about 10 impurity atoms per cm. on the entire surfaceof said wafer;

removing the wafer ends to divide the said higher conductivity surfaceregion into two separate zones adjacent said two major wafer faces;

removing a peripheral portion of said high conductivity surface regionadjacent the given conductivity type region of said water to expose aportion of said given conductivity type region; and,

attaching one electrical lead to the remaining portion of one majorface, attaching another electrical lead to the remaining portion of theother major face, and attaching another electrical lead to said exposedportion of said given conductivity type region.

4. A method of fabricating a high breakdown voltage transistorcomprising the following steps:

preparing a P-type monocrystalline germanium Wafer with two opposedmajor faces and two water ends;

masking said one major face;

difiusing antimony into the unmasked wafer face at a first and slow ratefrom an antimony source at a first and low concentration maintained at afirst and low temperature, so as to convert a surface zone of said waferto N-type conductivity and form a gradual junction therein, saidantimony source conconcentration and temperature being sufiicient toproduce a concentration of about 10 antimony atoms per cm. on saidunmasked wafer face;

removing the mask from said one major Wafer face;

diiiusing arsenic into said Wafer at a second rate greater than saidfirst diffusion rate from an arsenic source at a second concentrationgreater than said first source concentration and maintained at a sec ondtemperature higher than said first source temperature so as to convert athin surface region on both said major wafer faces to N-typeconductivity but higher conductivity than said surface zone, saidconcentration and temperature of said arsenic source being sumcient toproduce a concentration of about 10 arsenic atoms per 0111. on the Wafersurface;

removing the Water ends to divide the said higher conductivity surfaceregion into two separate zones adjacent said two major Wafer faces;

removing a peripheral portion of the arsenic-diffused high conductivityN-type surface region adjacent the P-type region or" said Wafer toexpose a portion of said P-type region; and,

attaching one electrical lead to the remaining portion of one majorwafer face, attaching another electrical lead to the remaining portionof the other major wafer face, and attaching another electrical lead tothe exposed portion of said given conductivity type region.

Reierences fired hy the Examiner UNITED STATES PATENTS BENJAMIN HENKIN,Primary Examiner. DAVID L. RECK, MARCUS U. LYONS, Examiners.

1. A METHOD OF FABRICATING A HIGH BREAKDOWN VOLTAGE TRANSISTORCOMPRISING THE FOLLOWING STEPS: PREPARING A GIVEN CONDUCTIVITY TYPEMONOCRYSTALLINE SEMICONDUCTIVE WAFER WITH TWO OPPOSED MAJOR FACES ANDTWO WAFER ENDS; DIFFUSING AN ACTIVE IMPURITY INTO SAID WAFER AT A FIRSTAND SLOW RATE FROM A FIRST AND LOW CONCENTRATION IMPURITY SOURCEMAINTAINED AT A FIRST AND LOW TEMPERATURE SO AS TO CONVERT A SURFACEZONE THEREOF ALL GROUND SAID WAFER TO OPPOSITE CONDUCTIVITY TYPE ANDFORM A GRADUAL JUNCTION THEREIN; REDUCING THE WAFER THICKNESS FROM ONESAID MAJOR WAFER TO ABOUT HALF THE ORIGINAL WAFER THICKNESS; DIFFUSINGAN ACTIVE IMPURITY INTO SAID WAFER AT A SECOND RATE GREATER THAN SAIDFIRST DIFFUSION RATE FROM A SECOND IMPURITY SOURCE AT A SECONDCONCENTRATION HIGHER THAN SAID FIRST IMPURITY SOURCE CONCENTRATION ANDMAINTAINED AT A SECOND TEMPERATURE HIGHER THAN SAID FIRST TEMPERATURE SOAS TO CONVERT A THIN SURFACE REGION ON BOTH SAID MAJOR WAFER FACES TOCONDUCTIVITY OF SAID OPPOSITE CONDUCTIVITY TYPE BUT HIGHER CONDUCTIVITYTHAN SAID SURFACE ZONE; REMOVING THE WAFER ENDS TO DIVIDE THE SAIDHIGHER CONDUCTIVE SURFACE REGION INTO TWO SEPARATE ZONES ADJACENT SAIDTWO MAJOR WAFER FACES; REMOVING A PERIPHERAL PORTION OF THE HIGHCONDUCTIVITY SURFACE REGION ADJACENT THE GIVEN CONDUCTIVITY TYPE REGIONOF SAID WAFER TO EXPOSE A PORTION OF SAID GIVEN CONDUCTIVITY TYPEREGION; AND, ATTACHING LEADS TO THE REMAINING PORTION OF EACH MAJOR FACEAND TO SAID EXPOSED PORTION OF SAID GIVEN CONDUCTIVITY TYPE REGION.